A) Field of the Invention
The present invention relates to a manufacture method for an insulated gate type field effect transistor having a lightly doped drain (LDD) structure.
B) Description of the Related Art
As a conventional manufacture method for an insulated gate type field effect transistor having an LDD structure, a method such as illustrated in FIG. 30 to 32 is known (for example, refer to JP-A-HEI-6-275635).
In a process shown in FIG. 30, after a field oxide film 2 having an element opening 2a is formed on one principal surface of a p-type semiconductor substrate 1, a gate insulating film 3 made of silicon oxide or the like is formed on the semiconductor surface exposed in the element opening 2a. After a polysilicon layer is deposited on the insulating film 3, the polysilicon layer is etched by using a resist layer 5 as a mask to leave a gate electrode layer 4 of polysilicon. In this case, the gate insulating film 3 just under the gate electrode layer 4 is left and the other gate insulating film is etched and removed.
Next, by using as a mask the resist layer 5, a lamination of the gate electrode layer 4 and gate insulating film 3 and the field insulating film, phosphorus ions are implanted into p-type substrate regions on both sides of the electrode layer 4 to form an n+-type source region 6 and an n+-type drain region 7.
In a process shown in FIG. 31, in the state that the gate electrode layer 4 is covered with the resist layer 5, the electrode layer 4 is isotropically etched to thin it through side etching. A width (gate width) of the electrode layer 4 is thinned, for example, to 0.8 μm to 0.5 μm.
In a process shown in FIG. 32, after the resist layer 5 is removed, by using as a mask a lamination of the gate electrode layer 4 and gate insulating film 3 and the field insulating film 2, phosphorus ions are implanted to form an n−-type source region 8 and an n−-type drain region 9 in the p-type substrate regions on both sides of the electrode layer 4. The drain region 9 is generally called an LDD region.